1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, to devices for the prevention of a floating gate condition in MOS logic circuits and processes for their manufacture.
2. Description of the Related Art
Referring to FIG. 1, a conventional Metal-Oxide-Semiconductor (MOS) logic circuit in the form of an inverter 10 is illustrated. Inverter 10 includes interconnected MOS transistors 12 and 14, and is capable of producing an output state (e.g., an output voltage) at the output node 16 in response to an input state (e.g., an input voltage) applied at the input node 18. The input node 18 is connected to the gates of the MOS transistors 12 and 14. In other words, the gates of these MOS transistors 12 and 14 are connected to each other to serve as the input node 18. For a further explanation of MOS inverters, see S. Wolf, Silicon Processing for the VLSI Era, Vol. 2--Process Integration, 373-376 (Lattice Press, 1990), which is hereby fully incorporated by reference.
Input node 18 is referred to as a "floating gate" since there is no electrical connection between the input node 18 (which is made up of the connected gates of MOS transistors 12 and 14) and either ground (GND) or the power supply voltage (V.sub.DD). In this regard, the term "floating gate" refers to the fact that the input state (i.e., input voltage) on the input node 18 and, therefore on the gates of the MOS transistors 12 and 14, is undefined and unknown. As a result, the output state produced by the inverter 10 at output node 16 is also undefined and unknown. Such an undesirable "floating gate" condition on the input node of an MOS logic circuit can be prevented by providing an electrical connection between the input node and either GND or V.sub.DD. Conventional semiconductor devices for this purpose can take the form of: (i) a resistor 20 connected between input node 18 of the MOS logic circuit and GND, as shown in FIG. 2; and (ii) an MOS transistor 30 with its gate connected to V.sub.DD, while its source is connected to input node 18 of the MOS logic circuit and its drain is connected to GND, as shown in FIG. 3.
The operation of conventional MOS logic circuits requires that a well defined logic state of either "0" or "1" be generated and applied to the input node of the MOS logic circuit by driving circuitry included within the MOS logic circuit. For example, a "0" or "1" logic state can be generated from the output node of another inverter or other MOS logic element. A logic state of "0" represents a voltage of essentially zero volts (e.g., GND or V.sub.SS) and is commonly referred to as a "low" state. A logic state of "1" represents a voltage of a magnitude significantly greater than that of the logic state of "0". The logic state of "1" is typically equal to V.sub.DD, and is generally referred to as a "high" state. If neither of these well defined logic states is applied to the input node of a MOS logic circuit, the input node of the MOS logic circuit can assume a random ambiguous state (i.e., an undefined state), thereby generating a random output state.
FIG. 4 illustrates an MOS logic circuit 40 wherein an inverter 42 is connected via its input node 44 to the output node 46 of driving circuitry 48 (which is illustrated for the purposes of this description as an MOS inverter). The input node 44 of inverter 42 and the output node 46 of driving circuitry 48 are also electrically connected to GND via resistor 50. A drawback of this configuration is that current is constantly consumed when the driving circuitry 48 is imposing a high logic state on the input node 44 of inverter 42. The path of this current consumption is shown by the dashed arrow in FIG. 4.
Still needed in the art is a semiconductor device that is capable of preventing a "floating gate" condition on an input node of a MOS logic circuit. The semiconductor device should also provide for reduced power consumption when the input mode of the MOS logic circuit is driven to a high state by driving circuitry. Also needed is a process for its manufacture that is simple and compatible with standard semiconductor device processing.